1. Technical Field
The present disclosure relates to a phase locked loop circuit and a gain calibration method thereof and, more particularly, to a phase locked loop circuit that uses a loop filter having a wide bandwidth for a fast lock time during a calibration operation and calibrates a gain of analog modulation data based on a frequency error accumulated in the loop filter after the loop filter is open, and a method of calibrating the gain of the phase locked loop circuit.
2. Discussion of Related Art
Wireless communications devices such as cellular phones, personal digital assistants PDAs), personal computers (PCs), and broadcast equipment include transceivers for transceiving data. The transceiver when operating as a transmitter modulates data to a radio frequency (RF) signal according to a particular wireless communication regulation or standard and outputs the RF signal.
When operating as a receiver, the transceiver receives the RF signal from another communication device and recovers the data by demodulating the received RF signal according to the particular wireless communications regulation or standard. In general, the transceiver of a wireless communication device includes a phase locked loop (PLL) circuit for generating a signal having a stable frequency for performing a precise frequency modulation or demodulation.
The PLL circuit is designed to have a bandwidth narrower than that of the modulation data in order to provide a low noise characteristic. Accordingly, the PLL circuit uses so-called two point modulation to cover the overall bandwidth of the modulation data. According to the two point modulation, digital modulation data (DMD) is applied to a dividing circuit of the PLL circuit and simultaneously analog modulation data (AMD) is additionally applied to a voltage controlled, oscillator. The PLL circuit is capable of performing the two point modulation.
FIG. 1 is a graph showing the frequency characteristic of a PLL circuit when only digital modulation data DMD is applied. Referring to FIG. 1, when only the digital modulation data DMD is applied, it is seen that the PLL circuit operates as a low pass filter.
FIG. 2 is a graph showing the frequency characteristic of a PLL circuit when only analog modulation data AMD is applied. Referring to FIG. 2, when only the analog modulation data AMD is applied, it is seen that the PLL circuit operates as a high pass filter.
FIG. 3 is a graph showing the frequency characteristic of a PLL circuit when both of the digital modulation data DMD and the analog modulation data AMD are applied. Referring to FIG. 3, it is seen that in this case the PLL circuit operates as an all pass filter.
When the gains of the two routes are mismatched, however, it can be seen that in the PLL circuit a frequency characteristic, such as gain, changes according to a frequency range. Thus, when the gains of the two routes are mismatched, a calibration operation is needed to maintain the frequency characteristic of the PLL circuit constant.